1 semicustom products UT90NHBD hardened-by-design (hbd) standard cell preliminary data sheet august 2014 www.aeroflex.com/radhardasic features ? up to 50,000,000 2-input nand equivalent gates with a 1.0v core using standard cell architecture ? toggle rates up to 5.0 ghz ? advanced 90nm silicon gate cmos processed in a com- mercial fab ? operating voltages: 2.5v and 1.8v i/o; 1.0v core ? radiation hardened from 100 krads(si) to 1 mrads(si) total dose available ? comprehensive set of core standard cells with multiple v t options for optimizing speed and power ? design support for mentor graphics?, synopsys?, verilog and vhdl design languages on sun (tm) and linux workstations ? power dissipation of 7nw/mhz/gate at v ddcore 1.0v and 20% duty cycle ? external chip capacitor att achment option available to space quality levels (for improved sso response) ? UT90NHBD asic technology is available under aero- flex?s accreditation of trust category 1a from design through device qualification and delivery. ? qml class y non-hermetic flip chip ceramic packaging ? standard microelectro nics drawing - 5962-14b01 product description the high-performance UT90NHBD hardened-by-design asic standard cell family features densities up to, and be- yond 50,000,000 equivalent nand2 gates. the deep submicron asic fami ly uses a highly efficient standard cell architect ure for the internal cell instantiation. combined with stat e-of-the-art place a nd route tools, the area utilization and signal interc onnect of transistors is max- imized using eight levels of copper metal interconnect. extensive cell library the UT90NHBD standard cell family is supported by an extensive cell library with over 900 elements. user select- able options for cell configurations include scan for all register elements, output drive strengths (1x to 30x) and transistor threshold voltages (lv t , rv t ). refer to aeroflex?s UT90NHBD design manual for complete cell listing and details. aeroflex gaisler ip we offer aeroflex gaisler processor ip. a complete library of aeroflex gaisler ip can be reviewed at www.aero- flex.com/gaisler.
2 i/o buffers the UT90NHBD library offers extensive i/o cell options. the i/o library contains 36 different general purpose cmos func- tional i/o pads. a rich set of lvds inputs and outputs support data rates up to 1.2gbps with optional on-chip terminations. the lvds family of buffers include several drive strengths for point-to-point, multi-point, and bus-lvds applications. the lvds buffers have programmable slew rate control. 2.5v and 1.8v lvds cells are available to optimize for speed and power in the system design. other i/o buffer features and options include: ? basic input, output, and bi-directional ? 9ma and 18ma drive strength ? slew rate control ? schmitt trigger ? tri-state ? open drain ? sstl 1.8v/2.5v cold sparing the UT90NHBDi/o library includes a set of cold sparing i/o cells that enables the user to design for system redundancy. these cold sparing cells present a high input impedance to the system interface when powered off assuring that the cold spared redundant device does not draw power. macro cells the UT90NHBD library includes a macro cell library that en- ables system-on-a-chip (soc) design. the following macros are currently available: ? clock generator pll ? 3.125 gbps serdes tx/rx lane ? 1, 2 and 4-lane 10 gbps serdes macro ? embedded die temperature resistor embedded sram aeroflex offers a comprehensiv e set of compiled embedded memories to meet your asic architectural needs. features include: ? single and dual port sram compiler ? single and two port register file compiler ? operating frequencies of 400mhz and higher ? optional edac rtl generation: 1 or 2 bit detect, 1 bit correct ? configurable word write mask ? optional integrated bist mux/collar ? all standard eda views supported clock driver distribution aeroflex design tools provide methods for balanced clock dis- tribution that maximize drive capability and minimize relative clock skew between clocked devices. the UT90NHBD pll?s all include optional external clock feed- back to support clock de-skew applications. speed and performance aeroflex specializes in high-per formance circuits designed to operate in harsh military and radiation environments. the UT90NHBD library offers cells in both regular vt and low vt allowing the user to trade spee d for power. the cells can be mixed on the same die providing local solutions for critical paths without sacrificing full chip power consumption. power dissipation and po wer estimation tools each internal gate or i/o driver has an average power consumption based on its switching frequency and capacitive loading. radiation-tolerant processes exhibit power dissipation that is typical of cmos processes. a power estimation spreadsheet that is useful for architecture trade-off analysis is available in the customer toolkit. for a more rigorous power estimating methodology, the synthesis library in the customer design toolkit supports pre-layout and post- layout power analysis. for additional information, refer to the aeroflex UT90NHBD design manual or consult with an aeroflex applications engineer. packaging both flip chip and wire bond packaging is available for the UT90NHBD asics. standard pin counts range from 624 to 1752 in both ceramic cgaand column attach options. heat sink and decoupling capacitors ar e available in the class y package.
3 "mentor graphics" is a registered trademar k of mentor graphics corporation. "synop sys" is registered trademark of synopsys, inc. in the united states and other countr ies. "sun" is a trademark or registered trademark of sun microsystems, inc. in the un ited states and other countries. all other company or product names ar e the registered trademarks or trademarks of their respective own- ers.
4 www.aeroflex.com info-ams@aeroflex.com our passion for performance is defined by three attributes represented by these three icons: solution-minded, performance-driven and customer-focused aeroflex colorado springs, inc., reserves the right to make changes to any products and services described herein at any time without notice. consult aeroflex or an authorized sales representa tive to verify that the information in this data sheet is current before using this product. aeroflex does not assume any responsibility or liability arising out of the application or use of any product or service described herein, ex cept as expressly agreed to in writing by aeroflex; nor does the purchase, lease, or use of a product or service fro m aeroflex convey a license under any patent rights, copyrights, trademark rights, or any other of the intellectual rights of aeroflex or of third parties. this product is controlled for export under the international traffic in arms regulations (i tar). a license from the u.s. government is required prior to the export of this product from the united states. aeroflex colorado springs - datasheet definition advanced datasheet - product in development preliminary datasheet - shipping prototype datasheet - shipping qml & reduced hi-rel
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